//Module to generate Card Information Structure (CIS). From C:\svn\firmware\picoe12\cis\Pico-E12.cis.

//------------- Version 3.4.3.x CIS for I/O based pico-E12 card.           -------------
//------------- Pico-E12.cis combines a parallel port and a memory tuple. -------------
//The CIS is divided into three parts:
//   1. The first is the general manufacturer information, including the long link tuple which
//      points to the subsequent parallel and memory CIS's.
//   2. The parallel port. This is provided to support JTAG for hardware and software debugging.
//   3. The memory window. This is used to access the Flash ROM and a variety of other services.
//   4. A bank of I/O control ports.
//
// NOTES: a. The number of address lines decoded by the parallel port MUST be three. Otherwise the
//           standard Microsoft driver parport.sys will not accept the interface.
//        b. The parallel port driver must occur first, otherwise XP get confused.
//        c. Both mode bits (8/16 bit I/O) must be set to 3. 3 means that the PCMCIA controller
//           will use 8 bit mode for out dx,al and 16 bit mode for out dx,ax. Otherwise WIN-2000
//           will use the mode bit for the first device (ie 8 bit always).
//        d. Installation under Win-2000 does not follow the normal procedure. Refer to the Pico Manual.
//        e. The checksum of this tuple appears to be 0x8359.
// Other than that is works as documented.

`include "PicoDefines.v"

module E12Tuple(addr, data);
input  [7:0]addr;
output [7:0]data;

reg    [7:0]rr;

always @(addr)
  case (addr)
//'Other Conditions' Device info tuple (type=01, length=06)
    8'h00: rr <= 8'h1C;  8'h01: rr <= 8'h07;
    8'h02: rr <= 8'h02;                                         //3.3V only operation
    8'h03: rr <= 8'h5F;                                         //Flash Memory Type with Extended Speed Byte
    8'h04: rr <= 8'h08;                                         //Device Speed = 1 nS (relies on wait line).
    8'h05: rr <= 8'h3E;                                         //Device Size  = 64 Mb (FE 11111 110 for 64MB Option, 7E 01111 110 for 32MB) -- wrong.
    8'h06: rr <= 8'h00;                                         //Also specify Parallel Port Interface
    8'h07: rr <= 8'h00;  8'h08: rr <= 8'hFF;                    //End of Tuple

//Manufacturer ID (type=20, length=04)
    8'h09: rr <= 8'h20;  8'h0A: rr <= 8'h04;
    8'h0B: rr <= 8'h41;  8'h0C: rr <= 8'h03;                    //Pico Manufacturer ID
    8'h0D: rr <= 8'h0C;  8'h0E: rr <= 8'hFF;                    //Product ID (E-12)

//Version Tuple (type=15, length=25)
    8'h0F: rr <= 8'h15;  8'h10: rr <= 8'h19;
    8'h11: rr <= 8'h04;                                         //PCMCIA Major Number
    8'h12: rr <= 8'h01;                                         //PCMCIA Minor Number
    8'h13: rr <= 8'h50;  8'h14: rr <= 8'h69;  8'h15: rr <= 8'h63;  8'h16: rr <= 8'h6F;
    8'h17: rr <= 8'h20;  8'h18: rr <= 8'h43;  8'h19: rr <= 8'h6F;  8'h1A: rr <= 8'h6D;
    8'h1B: rr <= 8'h70;  8'h1C: rr <= 8'h75;  8'h1D: rr <= 8'h74;  8'h1E: rr <= 8'h69;
    8'h1F: rr <= 8'h6E;  8'h20: rr <= 8'h67;  8'h21: rr <= 8'h00;//Name of Manufacturer = "Pico Computing"
    8'h22: rr <= 8'h45;  8'h23: rr <= 8'h2D;  8'h24: rr <= 8'h31;  8'h25: rr <= 8'h32;
    `ifdef IS_FX12
    8'h26: rr <= 8'h46;  8'h27: rr <= 8'h58;                    //Name of Product = "E-12FX"
    `else
    8'h26: rr <= 8'h4C;  8'h27: rr <= 8'h58;                    //Name of Product = "E-12LX"
    `endif
    8'h28: rr <= 8'h00;
    8'h29: rr <= 8'hFF;                                         //End of Product Info Tuple

//Function ID tuple (type=21, length=02). Required to keep XP happy !
    8'h2A: rr <= 8'h21;  8'h2B: rr <= 8'h02;
    8'h2C: rr <= 8'h00;                                         //Function ID = nuthing
    8'h2D: rr <= 8'h00;                                         //Function Mask: .01 = process in POST = 0, .02 = has expansion ROM = 0.

//Long Link MFC tuple (type=06, length=0B) pointing the subsequent memory and parallel tuples.
    8'h2E: rr <= 8'h06;  8'h2F: rr <= 8'h0B;
    8'h30: rr <= 8'h02;                                         //Number of subordinate tuples.
    8'h31: rr <= 8'h00;                                         //CIS Target address space for first function (00 - Attribute, 01 - Common)
    8'h32: rr <= 8'h3C;  8'h33: rr <= 8'h00;  8'h34: rr <= 8'h00;  8'h35: rr <= 8'h00;//Location of CIS#1
    8'h36: rr <= 8'h00;                                         //CIS Target address space for second function (00 - Attribute, 01 - Common)
    8'h37: rr <= 8'h5B;  8'h38: rr <= 8'h00;  8'h39: rr <= 8'h00;  8'h3A: rr <= 8'h00;//Location of CIS#2

    8'h3B: rr <= 8'hFF;                                         //End of CIS #0 (the long link chain).

//0x3C: Link Target(type=13, length=03) ------- CIS#1 describes parallel (JTAG) port ------------
    8'h3C: rr <= 8'h13;  8'h3D: rr <= 8'h03;  
	 8'h3E: rr <= 8'h43;  8'h3F: rr <= 8'h49; 8'h40: rr <= 8'h53;//CIS

//funcid parallel_port tuple (type=21, length=02)
    8'h41: rr <= 8'h21;  8'h42: rr <= 8'h02;
    8'h43: rr <= 8'h03;                                         //Function ID = parallel port
    8'h44: rr <= 8'h00;                                         //Function Mask: .01 = process in POST = 0, .02 = has expansion ROM = 0.

//PC card configuration tuple (type=1A, length=06)
    8'h45: rr <= 8'h1A;  8'h46: rr <= 8'h06;
    8'h47: rr <= 8'h05;                                         //TPCC_RASZ (.03 bits) = #bytes in TPCC_RADR = 1+1,
//TPCC_RMSZ (.3C bits) = #bytes in TPCC_RMSK = 1+1
    8'h48: rr <= 8'h01;                                         //TPCC_LAST = last config entry = 1
    8'h49: rr <= 8'h00;  8'h4A: rr <= 8'h02;                    //base address = 0x200
    8'h4B: rr <= 8'h01;  8'h4C: rr <= 8'h00;                    //configuration presence register = COR register (reg 0) is .0001 bit.
//0x0060 bits = IO base registers 10 & 12.

//Configuration Entry tuple #1. (type=1B, length=0A) Parallel Port
    8'h4D: rr <= 8'h1B;  8'h4E: rr <= 8'h0A;  8'h4F: rr <= 8'hC1;//_INDX  Config desc:    .40 = is default
//.80 = TPCE_IF present 
//.3F = configuration index = 1
    8'h50: rr <= 8'h81;                                         //_IF: bvd=0 rdy=0 mwait=1 wp=0 interface type=1(I/O and memory)
    8'h51: rr <= 8'h19;                                         //_FS: Feature desc:     .03 = _PD description follows
//.08 = _IO description follows
//.10 = _IR description follows
    8'h52: rr <= 8'h09;                                         //_PD: Power Desc:       .01 = nomV follows
//.08 = staticI follows
    8'h53: rr <= 8'h35;                                         //nominalV = 3.0 Volt
    8'h54: rr <= 8'h35;                                         //staticI  = 30.0 MilliAmp 
    8'h55: rr <= 8'h63;                                         //_IO: I/O desc:         .60 = 3 (8/16 bit only), .1F = IoAddrLines = 3. NOTE: must be 3 courtesy of Microsoft !
    8'h56: rr <= 8'h70;                                         //_IR: IRQ desc:         .70 = mask, level, pulse
    8'h57: rr <= 8'hFF;  8'h58: rr <= 8'hFF;                    //host's IRQ signal mask = FF FF

    8'h59: rr <= 8'hFF;                                         //---- End of CIS#1 (parallel port tuple)
    8'h5A: rr <= 8'h00;                                         //NULL Tuple.

//0x5B: Link Target (type=13, length=03) ------ CIS #2 describes Flash ROM and IO interface ---------------
    8'h5B: rr <= 8'h13;  8'h5C: rr <= 8'h03;  
	 8'h5D: rr <= 8'h43;  8'h5E: rr <= 8'h49; 8'h5F: rr <= 8'h53;//CIS

//Function ID tuple (type=21, length=02)
    8'h60: rr <= 8'h21;  8'h61: rr <= 8'h02;
    8'h62: rr <= 8'h01;                                         //Function ID = Memory
    8'h63: rr <= 8'h00;                                         //Function Mask: .01 = process in POST=0, .02 = has expansion ROM=0.

//PC card configuration tuple (type=1A, length=06)
    8'h64: rr <= 8'h1A;  8'h65: rr <= 8'h06;
    8'h66: rr <= 8'h05;                                         //TPCC_RASZ (.03 bits) = #bytes in TPCC_RADR = 1+1,
//TPCC_RMSZ (.3C bits) = #bytes in TPCC_RMSK = 1+1
    8'h67: rr <= 8'h01;                                         //TPCC_LAST = last config entry = 1
    8'h68: rr <= 8'h70;  8'h69: rr <= 8'h02;                    //base address = 0x270
    8'h6A: rr <= 8'h01;  8'h6B: rr <= 8'h00;                    //configuration presence register = COR register (reg 0) is .0001 bit.
//0x0060 bits = IO base registers 10 & 12.

//Configuration Entry tuple #0. (type=1B link=0D) Flash ROM
    8'h6C: rr <= 8'h1B;  8'h6D: rr <= 8'h0D;  8'h6E: rr <= 8'hC1;//_INDX  Config desc:    .40 = is default
//.80 = TPCE_IF present
//.3F = configuration # = 1
    8'h6F: rr <= 8'h81;                                         //_IF: bvd=0 rdy=0 mwait=1 wp=0 interface type=1(I/O and memory)
    8'h70: rr <= 8'h69;                                         //_FS    Feature desc:   .03 = _PD description follows
//.08 = _IO descriptor follows
//.60 = _MS descriptor +windows follows.
    8'h71: rr <= 8'h01;  8'h72: rr <= 8'h35;                    //_PD    VCC desc:             nominal 3 volts
    8'h73: rr <= 8'h68;                                         //_IO    IO  desc:       .1F = 8 adr lines decoded, .60 = 3 (8/16 bit only)
    8'h74: rr <= 8'h78;                                         //_MS    MEM descriptor:
//.07 = 00 number of (length,address,host) descriptors = 0+1
//.18 = 18 size of length field  = 3 bytes
//.60 = 60 size of address field = 3 bytes
////8'h75: rr <= 8'h00;  8'h76: rr <= 8'h20; 8'h77: rr <= 8'h00;//002000*256 = size of address, ie 0x200000 = 4Mbytes
    8'h75: rr <= 8'h00;  8'h76: rr <= 8'h01; 8'h77: rr <= 8'h00;//000100*256 = size of address, ie 0x10000  = 64 Kbytes
    8'h78: rr <= 8'h00;  8'h79: rr <= 8'h00; 8'h7A: rr <= 8'h00;//000000*256 = base address,    ie 0x000000 (byte address)

    8'h7B: rr <= 8'hFF;                                         //---- End of CIS#2 (Flash ROM tuple chain)
    8'h7C: rr <= 8'h00;                                         //NULL tuple

    8'h7D: rr <= 8'hFF;                                         //---- CIS End
    default: rr <= 8'hFF;                                       //---- end of CIS. Fill with FF. ------
endcase

assign data[7:0] = rr[7:0];
endmodule
